1. Field of the Invention
The invention relates to a memory chip, and more particularly to a judgment circuit for judging that a memory chip is operating as a single memory die or one among stacked memory dies according to statuses of an option pad of the memory chip.
2. Description of the Related Art
FIG. 1 is a schematic view showing a 256 Mb memory chip. Referring to FIG. 1, the memory chip 1 comprises 23 address pads A0˜A22, an option pad OP, and a dummy pad NC. When the memory chip 1 operates as a single memory die, both of the option pad OP and the dummy pad NC are floating. A weak pulling high/low circuit on the inside of the memory chip 1 gradually pulls an internal node which is connected with the option pad OP to a high/low voltage level. In the following description, a weak pulling high circuit and a weak pulling high operation for the option pad OP are given as an example.
In some applications, at least two memory chips 1, as shown in FIG. 1, can be stacked to form a memory device. As shown in FIG. 2, a 512 Mb memory device 2 having two stacked memory chips 20 and 21 of 256 Mb is given as an example. Each of the stacked memory chips 20 and 21 has the same structure as the memory chip 1 of FIG. 1, and the dummy pad NC of the memory chip 1 serves as the 24th address pad A23 for addressing the two memory chips 20 and 21. The top memory chip 20 is stacked on the bottom memory chip 21, and a spacer 23 is therebetween. FIG. 3 is a schematic view showing connection between the address pads A0˜A23 of the memory chips 20 and 21. In order to clearly show the connection, the memory chips 20 and 21 are shown side by side, and, however, in practice, the top memory chip 20 is stacked on the bottom memory chip 21, as shown in FIG. 2. Referring to FIG. 3, the address pads A0˜A23 of the memory chip 20 are connected to the address pads A0˜A23 of the memory chip 21 at address pads A0′˜A23′ respectively. The memory chips 20 and 21 receive an address signal through the address pads A0′˜A23′.
In FIG. 3, the option pad OP of the top memory chip 20 is tied to a high voltage source VDD, and an internal node connected to the option pad OP thereof is thus at a high level. The option pad OP of the bottom memory chip 21 is tied to a low voltage source VSS, and an internal node connected to the option pad OP thereof is thus at a low voltage level. Thus, when the address pad A23′ receives a logic high signal (H), the top memory chip 20 is activated and the bottom memory chip 21 is inactivated. Contrarily, when the address pad A23′ receives a low signal (L), the bottom memory chip 21 is activated and the top memory chip 20 is inactivated.
Thus, one memory chip, such as the memory chips 20 and 21, can operate at three modes according to the status of its option pad. At the first mode, the memory chip operates as a single memory die when the option pad OP thereof is floating; at the second mode, the memory chip operates as a top memory die among two stacked memory dies when the option pad OP thereof is tied to the high voltage source VDD; and at the third mode, the memory chip operates as a bottom memory die among two stacked memory dies when the option pad OP thereof is tied to the voltage source VSS. At the three modes, the internal node connected to the option pad OP of the memory chip is weakly pulled high, strongly pulled high, and strongly pulled low respectively. According to the above description, when one memory chip operates at the first mode and the second mode, an internal node connected to an option pad OP of the memory chip is pulled high. Thus, when the internal node is at a high level, the memory chip itself can not determine that it is operating as a single memory die (first mode) or as a top memory die among two stacked memory dies (second mode). This situation may occur to one memory chip desiring to be a top memory die among two stacked memory dies, such as the top memory chip 20 in FIG. 2.
Assume that a weak pulling low circuit and a weak pulling low operation are applied for floating of the option pad OP. According to the above description, when one memory chip operates at the first mode and the third mode, an internal node connected to an option pad OP of the memory chip is pulled low. Thus, when the internal node is at a low voltage level, the memory chip itself can not determine that it is operating as a single memory die (first mode) or as a bottom memory die among two stacked memory dies (third mode). This situation may occur to one memory chip desiring to be a bottom memory chip among two stacked memory dies, such as the bottom memory chip 21 in FIG. 2.
Thus, it is desired to provide a judgment circuit for judging that a memory chip is operating as a single memory die or one among stacked memory dies.